Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are susceptible to damage when exposed to an electrostatic discharge (ESD) event. An ESD event may occur, for example, when a user who has accumulated electrostatic charge picks up a CMOS IC. The accumulated charge may cause an instantaneous voltage of a few thousand volts to appear across terminals of the IC. This voltage is large enough to cause permanent damage to CMOS transistors, such as by rupturing the gates of the transistors. Thereafter, the CMOS IC cannot function properly.
In order to prevent the damage caused by an ESD event, CMOS IC designers include ESD protection circuits adjacent to input and/or output IC terminals. These circuits typically include diodes to discharge a large voltage appearing on a signal terminal into a power supply terminal.
It is also important for ESD protection circuits to include power supply voltage rail clamps. These rail clamps are designed to quickly dissipate a voltage between the power and ground power supply voltage terminals built up during an ESD event. One known rail clamp circuit uses a conventional low voltage CMOS transistor and a trigger circuit that makes the low voltage CMOS transistor conductive during an ESD event to short the power and ground rails. While low voltage CMOS transistors are highly conductive during an ESD event, they suffer from relatively high leakage current during normal operation. A known alternative rail clamp circuit uses a dual gate oxide (DGO) transistor instead of the low voltage CMOS transistor. While the DGO transistor exhibits relatively low leakage during normal operation due to its high threshold voltage, it suffers from low conductivity when made to be conductive during an ESD event. Thus neither conventional low voltage transistors nor DGO transistors are ideal for an ESD rail clamp circuit.
What is needed then is an ESD protection circuit that has both relatively low leakage during normal operation and relatively high conductivity during an ESD event.